1. Field of the Invention
The invention relates to a physical layer interface arrangement adapted to an integrated circuit (IC) chip.
2. Description of Related Art
An IC chip, in most cases, includes a substrate (e.g., a silicon wafer) and an IC layered structure configured on an active surface of the substrate. Here, the “active surface” refers to the surface of the substrate on which the IC layered structure is configured. In general, the IC layered structure includes a plurality of internal elements (e.g., MOS transistors, inductors, capacitors, and so on), a plurality of dielectric layers, and a plurality of patterned metal layers. The dielectric layers and the patterned metal layers are stacked to one another. The patterned metal layers allow signals of the internal elements to be transmitted to the external, and vice versa. Despite the arrangement of the internal elements and the patterned metal layers in the IC chip, the signals must be transmitted to the external or transmitted into the IC chip through the outermost portion of the IC layered structure. The outermost portion of the IC layered structure includes a core area and a signal area surrounding the core area. Here, the core area supplies core power and core ground, and the signal area supplies signals. In addition, the signal area further includes a plurality of physical layer interfaces that are arranged in a single row in the periphery of the core area. Signals with different functions are respectively transmitted through the physical layer interfaces. That is to say, each of the physical layer interfaces acts as a bridge for electrical connection between internal elements and external elements, and transmits the signal with the specific function. Under certain circumstances, the signals with the same function can be transmitted through several physical layer interfaces together.
In the IC chip manufactured by applying flip chip package technology, each physical layer interface of the outermost portion of the IC layered structure includes a plurality of bump pads that are arranged in accordance with the design rule. Besides, each of the physical layer interfaces further includes a plurality of inner pads and a plurality of redistribution lines. The inner pads and the redistribution lines are located below corresponding bump pads and in the IC layered structure. The inner pads are arranged in a single row, and the redistribution lines electrically connect the bump pads to the corresponding inner pads, respectively.
When an individual IC chip performs more and more functions, an increasing number of bump pads are required for signal input or signal output. Additionally, with advancement of manufacturing technology, the dimensions of the patterned metal layers and the internal elements in the IC chip can be further reduced, i.e., the entire area of the IC layered structure can be reduced. Therefore, improvement of the IC chip design is necessary in compliance with the current trend.